UVM (Universal Verification Methodology)¶
UVM is an Accellera-standardized SystemVerilog class library plus a set of conventions for structuring a testbench. It doesn't add anything to the language — everything in UVM is built from the OOP concepts covered in SystemVerilog → OOP & Classes.
What UVM actually gives you, concretely:
- A standard component hierarchy (driver, monitor, sequencer, agent, env, test) so any engineer who knows UVM can navigate an unfamiliar testbench in minutes instead of days
- A factory mechanism for swapping implementations without editing/recompiling test code — see The Factory
- A phasing mechanism so components across an entire testbench build, connect, run, and clean up in a coordinated, simulator-independent order — see Phases
- A sequence mechanism for generating and layering stimulus independent of the driver that ultimately pins it to the DUT — see Sequences & Sequencers
- Register abstraction (RAL) for generating register/memory access code from a spec instead of hand-writing it — see Register Abstraction (RAL)
| Page | Covers |
|---|---|
| Testbench Architecture | The standard component hierarchy and why each piece is separate |
| Phases | build → connect → run → check → report, and why order matters |
| Sequences & Sequencers | Decoupling stimulus generation from stimulus driving |
| The Factory | Type/instance overrides without touching existing code |
| Register Abstraction (RAL) | Generated register-map access, front-door vs. back-door |
Version note
Examples target UVM 1.2 (the current IEEE 1800.2 standard). A few APIs differ from the older UVM 1.1d (e.g. some uvm_config_db and phase-objection details) — check your simulator's shipped UVM version if something doesn't compile as shown.