SystemVerilog for Verification

SystemVerilog (IEEE 1800) is really two languages layered on top of Verilog: a set of RTL-coding improvements, and a much larger verification-focused extension — object-oriented classes, constrained-random stimulus, functional coverage, and assertions.

This section covers only the verification-relevant subset — the part that UVM is actually built on and that you'll use directly when writing testbenches, whether or not you use UVM at all.

Page	Covers
Data Types	4-state logic, 2-state types, packed/unpacked arrays, and when each matters
OOP & Classes	Classes, handles vs. instances, inheritance, polymorphism, rand/constraints
Interfaces	Interfaces, modports, clocking blocks, and why they replace bare signal ports
Functional Coverage	Covergroups, coverpoints, cross coverage, and closing coverage in practice
Assertions (SVA)	Immediate vs. concurrent assertions, sequences, properties

None of this requires UVM — you can (and should) understand it as plain SystemVerilog first. UVM is a class library and set of conventions built on top of these language features, not a separate language.