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UVM & SystemVerilog Verification Docs

A practical reference for functional verification of digital designs using SystemVerilog and UVM (Universal Verification Methodology).

This isn't a language spec or a UVM class reference dump — there are already excellent ones of those. The goal here is to explain why the pieces fit together the way they do: why a driver and monitor are separate components, why the factory exists at all, why rand and constraints interact the way they do. Understanding the "why" is what actually transfers to a new codebase; memorizing API signatures doesn't.

Where to start

If you're new to verification or coming from a design (RTL) background:

  1. SystemVerilog → Data Types — the 4-state logic model and why it exists
  2. SystemVerilog → OOP & Classes — the object-oriented subset UVM is built on
  3. UVM → Testbench Architecture — how the pieces (driver, monitor, sequencer, agent, env) fit together

If you already know the basics and want a specific topic, use the nav or search (top right).

Scope

  • SystemVerilog — the verification-relevant subset of IEEE 1800: data types, OOP, interfaces, functional coverage, and assertions (SVA). Not a synthesis/RTL-coding guide.
  • UVM — testbench architecture, phasing, sequences, the factory, and register abstraction (RAL), based on the Accellera UVM class library.

More topics (constrained-random techniques, virtual sequences, formal-adjacent SVA, debug workflow) will be added over time.

Who this is for

Written from hands-on ASIC/DV experience. Code examples are illustrative — always check your simulator's UVM version and vendor documentation for anything version-sensitive (UVM 1.1d vs 1.2 has real behavioral differences in a few places, noted where relevant).